A known semiconductor storage device is called an embedded Dynamic Random Access Memory (eDRAM) integrated over a Large Scale Integration (LSI) made up of a logical circuit that includes a microprocessor, etc. The eDRAM is a DRAM that uses an MOS capacitor for retaining cell data and is configured to achieve high speed operation. The data storage mechanism in the DRAM involves accumulating cell data in an MOS capacitor that makes up a memory cell and controlling input and output of cell data to and from the MOS capacitor by an MOS transistor for switching.
In the DRAM, data is retained by setting a voltage of a plate line coupled to the MOS capacitor to a certain negative voltage.
Conventionally, in order to stabilize this negative voltage, a semiconductor storage device has two detectors, one for detecting when the plate voltage becomes smaller than a certain level and the other for detecting when the plate voltage becomes larger than a certain level (for example, Japanese Laid-open Patent Publication No. 2003-168293). In the semiconductor storage device, two detectors are almost always activated to maintain the level of the plate voltage at a certain negative voltage by increasing or decreasing the plate voltage when the plate voltage moves out of the desired range.
In the semiconductor device, disturbances caused at writing may cause a large shift in the plate voltage in the direction of a negative potential, thereby causing a data on the memory cell to be lost.
When the negative voltage is stabilized by using two detectors to prevent data loss due to disturbance at writing, the two detectors are substantially always in an activated state. Thus, in the conventional semiconductor device, increased power consumption is a drawback.